ECE 111
Advanced Digital Design Project
Spring 2009
University of California, San Diego


 

Class Information

  • Instructor: Prof. Bill Lin (billlin@ece.ucsd.edu). Office: 4310 Atkinson Hall.
  • TA: Chia-Wei Chang (chc019@ucsd.edu)
  • Class: Tu/Th 11am-12:20pm, CENTR 206 (changed from York 4050A)
Announcements
  • 06-08: Final Group Presentations are hold on June 11 (Thur) 12pm-3pm in EBU1 room 4309. The presentation order is as following:
    • 12:00-12:30 (Group F: Truong, Tommy; Mak, Jason Gar-Wai ): Storm-1 processor
    • 12:30-13:00 (Group E: Agsalon, Denard; Dizmang, James ): CUDA, TESLA, implementation
    • 13:00-13:30 (Group A: Bonakdar, Dustin ): NVIDIA TESLA
    • 13:30-14:00 (Group D: Li, Harris; Grant, William Shane ): Network on Chip routing
    • 14:00-14:30 (Group C: Cheung, Wai Hung; Prasad, Shrey ): Tilera 64 Processor
    • 14:30-15:00 (Group B: Hung, I-Chen; Edward Tran ): IBM Cell processer

  • 06-05: The Final Report is due on June 11 at 11:59pm and the Final Presentation is temporarily on June 11(Thur) 12pm-3pm.

  • 05-29: The Final Group Presentations will need to be re-scheduled, tentatively on June 11, 12, or 13th. Chia-Wei will be emailing you for time availability. Also, due to unexpected circumstances, the final (third) group meetings have been cancelled.

  • 05-28: Here is a conference talk from Prof. Lin on a scalable switch architecture.

  • 05-28: The schedule for the Third (final) Group Meetings has been posted here.

  • 05-19: Congratulations to the following teams for their best designs:
    • Minimum delay design (Group D: Harris Li, William Shane Grant):
      • Area = BELS + Flip-Flops = 11613 + 2169 = 13782
      • Clock period = 6.155ns
      • Total cycles for ciphertext 1 and 2 = 820 cycles
      • Performance = total cycles * period = 5 microseconds
    • Minimum area design (Group E: Denard Agsalon, James Dizmang):
      • Area = BELS + Flip-Flops = 4974 + 2328 = 7302
      • Clock period = 7.058ns
      • Total cycles for ciphertext 1 and 2 = 2082 cycles
      • Performance = total cycles * period = 14.7 microseconds

  • 05-13: For your "area" report, look at the "Cell Usage" section in the "Final Report" produced by the Xilinx synthesis tool. We will count the number of logic gates ("BELS") and the number of flip-flops and sum them up as the "total area". Please email Chia-Wei your synthesis reports when you turn in your design.

  • 05-13: For "performance", please indicate the "number of cycles you need to perform the encryption" (i.e. when "done = 1"), and please provide the timing report which will specify the clock speed.

  • 05-13: Please use Virtex 5 for your Xilinx synthesis.

  • 05-13: Second project group meeting Tue-Wed May 26-27. You should have a 5-10 page report written by Sun May 24 so that we have something substantive to discuss at our second project group meeting.

  • 05-13: Project 2 due date moved to Sun May 17 by 11:59 PM PDT.

  • 04-28: Project 2 due date moved to Tue May 5th.

  • 04-23: Two page project summary due Thu May 7th. Email to Chia-Wei the link or doc, and link this to your project web page as well.

  • 04-21: For Thursday Apr 23, we will have a discussion about architecture strategies for your Project 2.

  • 04-21: For Project 2, Design 1 just needs to Minimize Area, and Design 2 just needs to Minimize Area*Delay Product. No need to satisfy clock period constraints.

  • 04-18: On the final project page that is due by Tuesday April 21, it should at least at this point include
    • group member(s),
    • short description of your project,
    • list of (and links to) 10-15 references, and
    • links to your project 1 files.
    Please email Chia-Wei the link to your final project page.

  • 04-15: Our class location has been moved to CENTR 206.

  • 04-14: For Project 1, no need to turn in the testbench since one has been given to you.

    By Tuesday April 21, please email Chia-Wei the link to your final project page.

  • 04-13: Please download the Xilinx ISE Design Suite 10.1 (free for first 60 days) to synthesize the codes. It's only compatible with ModelSim-PE or PE-student version. Please choose the "Family" as "Automotive 9500XL", "Device" as "Automatic xa9500xl", "package" as "*" and "speed" as "-*".

  • 04-12: You can work on project 1, project 2, and the final project as a team of 2 or individually. If you cannot find a partner for project 1, please go ahead and work on it individually. You still have the option of working with a partner for project 2 and/or the final project.

  • 04-09: Project 1 is due Thu Apr 16th, and Project 2 is due Thu Apr 30th. Your projects must be emailed to Chia-Wei (chc019@ucsd.edu) before 11:59 PM PDT on these dates. See the Verilog project page regarding what to turn in.

    Here is a test-bench for Project 1.

    See the Project 2 page for the test-bench and module interface for Project 2.

  • 04-06: Xilinx on a 64 bit OS (provided by Shane). In case anyone has trouble installing Xilinx on a 64 bit OS, they can force the installer to install it by using the setup.exe in the /bin/nt/ folder (probably the same for linux under /bin/lin/. If they just run the normal setup in the root directory it will pick the 64 bit version which doesn't actually install everything needed.

  • 04-02: We will have class next Tue April 7th. Chia-Wei will do a demo of the Xilinx and ModelSim tools on some tutorial examples. Please install these software packages as soon as possible and try running through yourself the tutorial examples. I myself will see you in class next Thu April 9th.

    Please select 2-3 projects that you'd like to consider for you project. Please be prepared to say 3-4 sentences about it next Thu April 9th: 1) What do you think is different about the problem that you'd like to study vs. traditional or previous work? 2) The problem that you want to study, what problem do you think that effort trying to solve, and what's your impression on how they are addressing the problem, etc.

  • 03-31: Welcome to the first day of class. Some initial ideas for the final project are listed here. Start thinking about this as soon as possible so that you can come up with 2-3 problems that you want to work on.

    The Verilog project pages are up also, as well as links to download the Xilinx synthesis package and the ModelSim simulator.