ECE 111 Advanced Digital Design Project Spring 2009

University of California, San Diego

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Verilog Design Projects Please download the Xilinx ISE Design Suite 10.1 (free for the first 60 days) to synthesize the codes. It's only compatible with ModelSim-PE or PE-student version. Please choose the "Family" as "Automotive 9500XL", "Device" as "Automatic xa9500xl", "package" as "*" and "speed" as "-*". Tutorial for Project 1 Project 1 (due 11:59 PM PDT, Thu Apr 16) Project 1 introduction More description of Project 1 Here is a test-bench for Project 1: tb_fibonacci_calculator.v Two wave diagram examples: wave1 and wave2 Emailed to Chia-Wei (chc019@ucsd.edu) the following for your Project 1. Project 2 (due 11:59 PM PDT, Sun May 17) Overall project description Project 2 introduction Hints for Project 2 The test-bench and module interface are provided in the Project 2 page. The correct ciphertext is here: Ciphertext.dat. Emailed to Chia-Wei (chc019@ucsd.edu) the following for your Project 2.