Spring 2009 ECE 111 PROJECT 2

ECE 111 Project 2

Project Description

The goal of this project is to design the WEP Co-Processor, a HW block that speeds up the cryptographic computations in the MAC layer of the 802.11 Wireless LAN protocol.

1. Objectives:

Design 1: A design that is minimized for area.

Design 2: A design that is minimized for delay.

Report results as specified in Deliverables

2. Specification:

WEP implements a stream cipher symmetric key cryptographic algorithm (RC4) from RSA Data Security. Since RC4 is proprietary, for this project, our design of the WEP co-processor will use a public algorithm (known as ARCFOUR) instead of RC4 (a Google search on RC4 will tell you about how the RC4 code "leaked" onto the internet). To understand the algorithm that must be implemented, go over:

Project 2 HW Specification (from Lecture)
Reference C implementation.(*****) When compiled and run this C program will generate the ciphertext that you should obtain. To compile the file, use the command, gcc wep_test.c; to run the executable, use the command, a.out
An Internet draft on ARCFOUR

This Verilog Module Interface (*****) contains the WEP Co-processor declaration and explanation of each port:

3. Testbench:

Use this testbench (*****) and plaintext.dat (*****) file used by the testbench to help verify your design. Note, it is imperative that your design passes the testbench, otherwise, Project 3 will turn into a nightmare. Feel free to modify the testbench to test your design more thoroughly. However, you will be graded only on the basis of the provided testbench.

This is the timing diagram (*****) for reading and writing to the DPSRAM. It is a conservative timing model; however please use this in order to ensure correctness of the design (in the presence of, say, clock skew etc).

Part A: Minimize Area

State machine diagram
Verilog code for the Co-processor
ModelSim scripts and traces. Illustrate clearly that your design passes the testbench.
Results of synthesis: (a) Synthesis script that you used (b) Area, timing and resource reports. (c) Include warnings (if any).
Area occupied by the design

Part B: Minimize Delay

State machine diagram (if different from Part A)
Verilog code for the Co-processor (if different from Part A)
ModelSim scripts and traces. Illustrate clearly that your design passes the testbench.
Results of synthesis: (a) Synthesis script that you used (b) Area, timing and resource reports. (c) Include warnings (if any).
Performance report: Measure time taken by your design to encrypt the data provided by the testbench.

Delay (ns) = no. of clock cycles (measured from simulation) * Clock Cycle Time (ns, obtained from synthesis)
Area occupied by the design
Area*Delay value

Compare the number and types of adders and the number of muxes for the two synthesis results in part A and part B. Examine the sample synthesis scripts to see which commands will generate information that will be helpful in accomplishing this.