module lab4 (datain, clock, reset, startbit, onebit, zerobit);

        input datain;
        input clock, reset;
		output startbit;
		output onebit;
		output zerobit;
			
		//declare/redeclare all registers
        reg[11:0] temp; //a temporary shift register used to store data
		reg startbit;
		reg onebit;
		reg zerobit;
///////-----------------behavioral code------------------//////////		  			
		always @ (temp) //continuous assignment, temp is only item in sensitivity list.
			if (temp == 12'b100000000001) startbit = 1; //if the given pattern is found, set the startbit to zero
			else if (temp[10:0]== 11'b10000000001)  //finish this line
			else if (temp[6:0]== 7'b1000001)  onebit = 1; 
			else if //finish this line
			else if //finish this line
			else if //finish this line
			else 
				begin
					zerobit = 0;  //if temp register does not follow pattern, set to zero
					onebit = //finish this line
					startbit = //finish this line
				end
			
        always @(posedge clock)//this is standard code for a 12 bit shift register
			begin
			if (reset) temp = //finish this line
			else temp= {temp[??:0],??}; //finish this line (fill in the ??)
			end
//////////////////////////////////////////////////////////
endmodule