module lab5(clock, reset, onebit, zerobit, startbit, sel1, ld1, ld2, ld3, ld4, ld5, ld6);
    input reset;
    input clock;
    input sel1;
    input onebit;
    input zerobit;
    input startbit;
    output ld1, ld2, ld3, ld4, ld5, ld6;
    //output [11:0] outreg;     we will not be using this output, it may be beneficial for debugging
	 
	reg[11:0] outreg; //bit 0 is oldest bit, bit 11 is newest
	reg ld1, ld2, ld3, ld4, ld5, ld6;
	 
////----------------behavioral code------------------///////		
	always @ ( posedge clock ) 
		begin		
		


			//Put your code here



		end
		
	always @ (sel1 or outreg) //standard mux with selector and register on sensitivity list.
		begin
		


			//Put your code here


		end
		
endmodule